Xilinx Vivado Design Suite 2019.1 ISO
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Xilinx Vivado Design Suite 2019.1 ISO | 21.4 GB
Vivado Design Suite HLx Editions - Accelerating High Level Design. Vivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.
The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.
Accelerating High Level Design
- Software-defined IP Generation with Vivado High-Level Synthesis
- Block-based IP Integration with Vivado IP Integrator
- Model-based DSP Design Integration with System Generator for DSP
Accelerating Verification
- Vivado Logic Simulation
- Integrated Mixed Language Simulator
- Integrated & Standalone Programming and Debug Environments
- Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS
Accelerating Implementation
- 4X Faster Implementation
- 20% Better Design Density
- Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end
Production devices
Space-Grade Kintex UltraScale:- XQRKU060
XA Kintex-7:- XA7K160T
Virtex UltraScale+ HBM (-3 speedgrades):- XCVU31P, XCVU33P, XCVU35P, XCVU37P
Vivado
Command line based web-installer
Enhanced VHDL2008 synthesis construct support
Integrated GitHub download of 3rd party boards
Congestion metrics, Improved QOR suggestions as well as general SSI QOR improvement
Enhanced debug capabilities: IBERT GTM, RF Analyzer, HBM Monitor and Bus Description view
IP Subsystems/Cores
New 50G RS-FEC (544,514):New FEC (2x26G) NRZ used for 5G wireless applications to enable PAM-4 applications when adding an external bitmux chip
Integrated UltraScale/UltraScale+ 100G Ethernet Subsystem: New optional AXI data bus interface allowing standard based interface
10G/25G Ethernet Subsystem, 40G/50G Ethernet Subsystem, Integrated UltraScale/UltraScale+ 100G Ethernet Subsystem, USXGMII, 1G/10G/25G Ethernet Switching Subsystem: Size optimized statistic counter by creating statistics logic based on features selected
Video and Imaging IPs: Video processing cores add support for 8K30 resolutions; Video mixer adds 16 layer mixing; Framebuffers adds support for 12 and 16bpc
SmartConnect: Improved area efficiency, especially for small configurations and AXILite endpoints
AXI Bram Controller:Improved performance for single beat transactions. Configurable read latency for tight timing margins.
System Requirements:
Windows 7 SP1 (64-bit)
Windows 8.1 (64-bit)
Windows 10 Pro (64-bit)
Xilinx.Vivado.Design.Suite.2019.1.ISO-TBE
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